1. Field of the Invention
The present invention relates to a method for forming a metal plug on a semiconductor wafer.
2. Description of the Prior Art
On a semiconductor wafer there is always a dielectric layer between the metallic layers that is used to isolate and protect the conductive lines on the semiconductor wafer. In order to electrically connect every metallic layer to form a complete circuit, it is necessary to form a metal plug between metallic layers that serves as an electrical path connecting the conductive lines of each layer. Improving the quality of the process for forming metal plugs is a very important issue in semiconductor processing research.
Please refer to FIG. 1 to FIG. 9. FIG. 1 to FIG. 9 are cross-sectional diagrams of the process of forming a metal plug 46 on the semiconductor wafer 10 according to the prior art. As shown in FIG. 1, the semiconductor wafer 10 comprises a substrate 12, a field oxide layer 14 installed in a predetermined area on the surface of the substrate 12, two polysilicon layers 16 separately installed over the substrate and the field oxide layer 14, a dielectric layer 18 installed on the surface of the substrate 12 and covering the polysilicon layers serving as an insulation layer between the two polysilicon layers 16, two via holes 20 installed in the dielectric layer 18 above the polysilicon layers 16, and a conductive layer 22 installed over the dielectric layer 18 and filling the via holes 20.
The prior art method of forming a metal plug is to first perform a lithographic process to form a photo-resist layer 24 on the conductive layer 22. As show in FIG. 1, the photo-resist layer 24 comprises three opening 26 to define the positions of two contact plugs. As shown in FIG. 2, a dry etching process is performed to etch the conductive layer 22 under the openings 26 down to the surface of the dielectric layer 18. As shown in FIG. 3, the photo-resist layer 24 is then completely removed. The remaining conductive layer 22 will form two contact plugs 28 that connect between the polysilicon layers 16 and a subsequent metallic layer (not shown).
After completing the contact plugs 28, a planarization process is performed. First, a plasma enhanced chemical vapor deposition (PECVD) process is performed to form a dielectric layer 30 of silicon dioxide (SiO.sub.2) to completely cover the surfaces of the conductive layer 22 and the dielectric layer 18, as shown in FIG. 4. A spin-on glass (SOG) process is then performed to form an SOG layer 32 on the surface of the dielectric layer 30, filling the gaps between the contact plugs 28. As shown in FIG. 5, an etch back process uniformly removes part of the SOG layer 32 to reduce its thickness. Then, a PECVD process forms a dielectric layer 34 of silicon dioxide on the surface of the semiconductor wafer 10, completing the planarization process of the semiconductor wafer 10. The dielectric layer 30, SOG layer 32, and the dielectric layer 34 form a sandwich-type structure that guarantees the physical and chemical characteristics of the SOG layer 32.
As shown in FIG. 6, a lithographic process is performed to form a photo-resist layer 36 above the dielectric layer 34, the photo-resist layer 36 comprising two openings 38 that are used to define the position of a metal plug 46. As shown in FIG. 7, a wet etching process, along the openings 38, etches the dielectric layer 34 downward. Two bowl-like via holes 40 are formed because of the isotropic nature of the wet etching process. As shown in FIG. 8, an anisotropic etching process is performed to etch downwards through the dielectric layer 34, SOG layer 32, and the dielectric layer 30 so as to form two via holes 42 below the via holes 40. The via holes 40 and via holes 42 together form a wineglass-shaped structure. As shown in FIG. 9, the photo-resist layer 36 is then completely removed. A metallic conductive layer is formed on the dielectric layer 34, filling the via holes 40 and via holes 42 to form a metal plug 46.
The prior art method of forming the metal plug 46 requires first forming via holes 40 and via holes 42 and then filling them with metal to electrically connect the conductive layer 44 to the conductive layers 22. The prior art method of forming the metal plug 46 has several shortcomings, as follows:
(1) The via hole 42 has a large aspect ratio and is therefore not easy to fill with metal. Voids often form in the metal plug, affecting its electrical performance. This problem becomes more serious in sub-micron processes. PA1 (2) The diameter of each via hole is getting smaller with the reduction of component sizes. When performing the lithographic process to define each via hole, misalignment can easily occur. To completely fill the via holes, most via holes possess a wineglass-shaped structure. However, the bowl-like structure of the via hole reduces misalignment tolerances, and it is easy to destroy other components and cause component shorts when forming the bowl-like structure. PA1 (3) Currently, the metal plug 46 is mostly formed using tungsten plug (W-plug) technology. Although tungsten has nice step coverage abilities that resolve the problem of gap filling, it increases both the resistance of the metal plug 46 and the production cycle time. Furthermore, the tungsten plug technology is not very economical. PA1 (4) When forming the via hole 42, the polymers produced for etching the SOG layer 32, and the dielectric layers 30, 34 cannot be completely removed, which may further complicate the problem of filling metal into the via holes. PA1 (5) The prior art method performs a planarization process on the surface of the semiconductor wafer 10 to increase the accuracy of the follow-up metal conductive lines processes. However, the SOG layer 32 of the planarization process can absorb moisture. When filling metal into the via holes 40, 42, the moisture may leak into the via holes 40, 42 and adversely affect the process, resulting in so-called poison vias. PA1 (6) When using the tungsten plug technology to form the metal plug 46, because tungsten has poor adhesion to other materials, a titanium nitride (TiN) layer or an alloy layer of titanium and tungsten will usually be added between the tungsten plug and the follow-up metal to be used as a barrier layer to promote the adhesion of the tungsten. However, this barrier layer increases the resistance of the metal plug 46 and affects the performance of the entire component.